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Designing Hardware With Software: Hardware Description Languages

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Designing Hardware With Software: Hardware Description Languages

Use your coding skills to implement high-performance functionality in FPGA hardware.

· IoT Zone ·
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Here's an idea: Use your software development skills to learn how to define a digital circuit in a hardware description language. You can program your design into a field-programmable gate array, resulting in a fully functional, high-performance custom digital device. Low-cost FPGA prototyping boards contain sufficient logic elements to implement complex modern processor designs such as RISC-V, along with any customized extensions you dream up.

Hardware description languages are not the exclusive province of digital designers at semiconductor companies; even hobbyists can make full use of these powerful, free tools. This article introduces the VHDL language, used widely in the development of FPGA circuit designs.

Logic Gates

Before we get to VHDL, we'll take a quick look at the basics of digital circuits. Inside the integrated circuit chip, a computer processor is constructed from transistors, resistors, capacitors, and other circuit elements. One level up the abstraction hierarchy, digital circuits implement logic gates to perform simple operations such as NOT, AND, OR, and XOR.

A NOT gate inverts its input (an input of 1 produces and output of 0 and vice versa). An AND gate has an output of 1 only when both of the A and B inputs are 1, otherwise the output is 0. An OR gate has an output of 1 when either or both of the A and B inputs are 1. An XOR gate has an output of 1 only when exactly one of the A and B inputs is 1. The schematic symbols for these components are shown here:

Logic gate schematic symbols

By combining logic gates, you can develop more complex digital circuits, such as registers and adders, and ultimately an entire processor.

Single-Bit Adder Circuit

It is straightforward to represent simple digital circuits using logic diagrams. For example, an adder circuit adds two data bits (A and B) plus an incoming carry (Cin) and produces a one-bit sum (S) and a carry output (Cout). This is called a full adder because it includes the incoming carry in the calculation. A half adder adds only the two data bits without the incoming carry.

Full adder

This diagram can be condensed to a schematic block with three inputs and two outputs for use in higher level diagrams. The next figure represents a 4-bit adder that contains four copies of the full adder circuit. The inputs are the two words to be added, A0-A3 and B0-B3, and the incoming carry, Cin. The output is the sum, S0-S3, and the outgoing carry, Cout.


4-bit adder

When designing digital devices of greater complexity than these examples, the use of logic diagrams quickly becomes unwieldy. As an alternative to the logic diagram, a number of hardware description languages have been developed over the years. This evolution has been encouraged by Moore's Law, which drives digital system designers to continually find new ways to quickly make the most effective use of the constantly growing number of transistors available in integrated circuits.

FPGAs

A gate array is a logic device containing a large number of logic elements that can be connected to form arbitrary digital circuits. A category of gate arrays called field programmable gate arrays (FPGAs) enables end users to implement their own designs into gate array chips using just a computer, a low-cost prototyping board, and an appropriate software package.

VHDL

VHDL is one of the leading hardware description languages in use today. Development of the VHDL language began in 1983 under the guidance of the U.S. Department of Defense. The syntax and some of the semantics of VHDL are based on the Ada programming language. Verilog is another popular hardware design language with capabilities similar to VHDL. Chisel, an extension of the Scala programming language, provides advanced digital circuit design and reuse capabilities for major digital development efforts such as the open-source RISC-V processor.

VHDL is a multilevel acronym where the V stands for VHSIC, which means Very High-Speed Integrated Circuit, and VHDL stands for VHSIC Hardware Description Language. The following code is a VHDL implementation of the full adder logic diagram shown above:

VHDL
 




xxxxxxxxxx
1
27


 
1
-- Load the standard libraries
2
 
          
3
library IEEE;
4
  use IEEE.STD_LOGIC_1164.ALL;
5
 
          
6
-- Define the full adder inputs and outputs
7
 
          
8
entity FULL_ADDER is
9
  port (
10
    A     : in    std_logic;
11
    B     : in    std_logic;
12
    C_IN  : in    std_logic;
13
    S     : out   std_logic;
14
    C_OUT : out   std_logic
15
  );
16
end entity FULL_ADDER;
17
 
          
18
-- Define the behavior of the full adder
19
 
          
20
architecture BEHAVIORAL of FULL_ADDER is
21
 
          
22
begin
23
 
          
24
  S     <= (A XOR B) XOR C_IN;
25
  C_OUT <= (A AND B) OR ((A XOR B) AND C_IN);
26
 
          
27
end architecture BEHAVIORAL;



This code is a fairly straightforward textual description of the full adder circuit. Here, the section introduced with entity FULL_ADDER (line 8) defines the inputs and outputs of the full adder component. The architecture section (line 20) describes how the circuit operates to produce the outputs S and C_OUT given the inputs A , B , and C_IN . The term std_logic refers to a single-bit binary data type. The <= character sequence represents a wire-like connection, driving the output on the left-hand side with the value computed on the right-hand side.

The following code references the FULL_ADDER as a component in the implementation of the circuit shown in the 4-bit adder logic diagram:

VHDL
 




x
1
76


 
1
-- Load the standard libraries
2
 
          
3
library IEEE;
4
  use IEEE.STD_LOGIC_1164.ALL;
5
 
          
6
-- Define the 4-bit adder inputs and outputs
7
 
          
8
entity ADDER4 is
9
  port (
10
    A4        : in    std_logic_vector(3 downto 0);
11
    B4        : in    std_logic_vector(3 downto 0);
12
    SUM4      : out   std_logic_vector(3 downto 0);
13
    C_OUT4    : out   std_logic
14
  );
15
end entity ADDER4;
16
 
          
17
-- Define the behavior of the 4-bit adder
18
 
          
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architecture BEHAVIORAL of ADDER4 is
20
 
          
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  -- Reference the previous definition of the full adder
22
 
          
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  component FULL_ADDER is
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    port (
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      A             : in    std_logic;
26
      B             : in    std_logic;
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      C_IN          : in    std_logic;
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      S             : out   std_logic;
29
      C_OUT         : out   std_logic
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    );
31
  end component;
32
 
          
33
  -- Define the signals used internally in the 4-bit adder
34
  signal c0, c1, c2 : std_logic;
35
 
          
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begin
37
 
          
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  -- The carry input to the first adder is set to 0
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  FULL_ADDER0 : FULL_ADDER
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    port map (
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      A          => A4(0),
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      B          => B4(0),
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      C_IN       => '0',
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      S          => SUM4(0),
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      C_OUT      => c0
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    );
47
 
          
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  FULL_ADDER1 : FULL_ADDER
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    port map (
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      A          => A4(1),
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      B          => B4(1),
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      C_IN       => c0,
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      S          => SUM4(1),
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      C_OUT      => c1
55
    );
56
 
          
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  FULL_ADDER2 : FULL_ADDER
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    port map (
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      A          => A4(2),
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      B          => B4(2),
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      C_IN       => c1,
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      S          => SUM4(2),
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      C_OUT      => c2
64
    );
65
 
          
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  FULL_ADDER3 : FULL_ADDER
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    port map (
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      A          => A4(3),
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      B          => B4(3),
70
      C_IN       => c2,
71
      S          => SUM4(3),
72
      C_OUT      => C_OUT4
73
    );
74
 
          
75
end architecture BEHAVIORAL;



Here, the section introduced with entity ADDER4 (line 8) defines the inputs and outputs of the four-bit adder component. The phrase std_logic_vector(3 downto 0) represents a four-bit data type with bit number 3 in the left-hand (most significant) position and bit number 0 on the right-hand side.

The FULL_ADDER component is defined in a separate file, referenced here by the section beginning component FULL_ADDER is (line 23). The statement signal c0, c1, c2 : std_logic; (line 34) defines the internal carry values between the full adders. The four port map sections (lines 39-73) define the connections between the 4-bit adder signals and the inputs and outputs of each of the single-bit full adders. To reference a bit in a multi-bit value, the bit number follows the parameter name in parentheses. For example, A4(0) refers to the least significant of the four bits in A4.

Hierarchical Design

Note the use of hierarchy in this design. We defined a simple component, the single-bit full adder, as a discrete, self-contained block of code. We then used this component to construct a more complex circuit, the four-bit adder. This hierarchical approach can be extended through many levels to define an extremely complex digital device constructed from less complex components, each of which, in turn, is constructed from even simpler parts.

This general approach is used routinely in the development of modern processors containing billions of transistors, while managing complexity in a manner that keeps the design understandable by humans at each level of the architecture.

The code in these listings provides all the information a logic synthesis software tool suite requires to implement the four-bit adder within an FPGA device.

Summary

This has been a very brief introduction to VHDL. The intent here is to make you aware that hardware description languages such as VHDL are the current state of the art in complex digital circuit design, and that these capabilities are available for your use. In addition, you should know that some very low-cost options are available for FPGA development tools and devices.

This article is adapted from my new book, Modern Computer Architecture and Organization, published by Packt Publishing. The book includes chapter exercises that get you started with VHDL development using freely available tools. These exercises, along with example VHDL solutions, are available at the book GitHub repository.

Topics:
hardware development, hardware hacking, iot, languages, tutorial

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