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Screw the Recession: Intel

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Screw the Recession: Intel

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With the economy gripped by fears of recession, nobody knowing how deep this mortgage crisis thing is going to run and the American consumer snapping his pocketbook shut, it seems a heck of a time to try to invent a new category of consumer widgets. But Intel has this tiny new low-power, battery-preserving, single-core, 45nm Silverthorne chip that it’s gotta do something with. In fact, as CEO Paul Otellini indicated at the Consumer Electronics Show last month Intel’s hoping to make a killing on sub-$400 web-in-your-pocket devices, what it calls Mobile Internet Devices (MIDs), stuff like GPS devices.

Anyway, according to what Intel just disclosed at the International Solid State Circuits Conference (ISSCC), Silverthorne, which is slated to arrive in these newfangled – ARM-based iPhone-inspired – MIDs in the second quarter, slides in between what you’d put in a smartphone and what you’d use for a notebook PC, a step, it would appear, before Intel goes full bore after the next-generation phone market and reuses the technology in other parts for other segments – even servers.

Despite its diminutive 25mm-squared size, Silverthorne is still fully compatible with the Core 2 Duo instruction set – including hyperthreading and virtualization – so it can look like two cores – and should be good for 2GHz while consuming only a watt of power – well, eventually at any rate. It runs 0.6W-2W and its performance has been compared to a five-year-old Pentium M (Banias).

What’s different about Silverthorne is its old-fashioned “in order” execution, which carries out instructions one at a time, rather than the performance-enhancing “out-of-order” execution that chips use these days that executes instructions any which way. This helps reduce Silverthorne’s power demands to a tenth of what Intel’s ultra-low-power processors needed in 2006 .

So does a sleep state management technique called Deep Power Down, non-grid clock distribution, power-optimized register-file, clock gating, CMOS bus mode and a split I/O power supply, which should cut down on power leakage.

Hyperthreading will make up for some of the performance loss by letting Silverthorne work on two instructions at a time.

Silverthorne fits into the Menlow platform that’s already sampled. That includes the Paulsbo chipset. Silverthorne has a 512KB cache and a 533MHz front-side bus.

Via expects its competitive new x86 Isaiah chip to outperform Silverthorne. Isaiah uses the out-of-order technique and has a much bigger cache and faster bus.



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